The present disclosure relates to a semiconductor device and, more particularly, to a semiconductor device in which a semiconductor identifier is set after layering in a multilayer semiconductor device and a multilayer semiconductor device formed by layering two or more such semiconductor devices.
For an integrated semiconductor device, a multilayer semiconductor device formed by layering two or more semiconductor chips for three-dimensional configuration is known. The semiconductor chips layered in such a multilayer semiconductor device are interconnected with common wiring, such as a bus, for example. This common wiring is hereafter referred to also as global wiring.
When global wiring is employed, control signals generated by a logic and the like are simultaneously transmitted to two or more semiconductor chips via global wiring. Therefore, selective access to one specific semiconductor chip requires for this semiconductor chip to recognize whether or not a signal outputted from the logic and the like is addressed to this semiconductor chip for each multilayer semiconductor chip. Accordingly, the semiconductor chip concerned is able to operate in accordance with a signal addressed to this semiconductor chip. If a signal is found not addressed to the semiconductor chip, this semiconductor chip is able to operate not to respond such a signal.
Therefore, in order to allow the selective control of each semiconductor chip, a technique is in use in which a chip identifier is allocated to each of the chips that are layered. This facilitates the construction of a mechanism for controlling only particular semiconductor chips by specifying their chip identifiers.
For the above-mentioned chip identifier allocation, a related-art technology is known in which a chip identifier is held in a nonvolatile memory or a member equivalent thereto in each semiconductor chip (see Japanese Patent Laid-open No. 2003-110086 (FIG. 3) referred to as Patent Document 1 hereinafter and Japanese Patent Laid-open No. Hei 7-283375 (FIG. 2) referred to as Patent Document 2 hereinafter, for example).
In another related-art technology, a chip identifier is set by wiring predetermined two or more terminals to power or ground at the time of package assembly (see Japanese Patent Laid-open No. 2005-25864 (FIG. 3) referred to as Patent Document 3, for example).
In still another related-art technology, a chip identifier is set in accordance with the fluctuation or each semiconductor chip or the fluctuation of a particular characteristic (see Japanese Patent Laid-open No. 2006-190840 (FIG. 2), Japanese Patent Laid-open No. 2009-147088 (FIG. 1), Japanese Patent Laid-open No. 2005-122823 (FIG. 3), referred to as Patent Documents 4 to 6, for example).
In yet another related-art technology, an increment circuit arranged for each semiconductor chip is sequentially connected with other increment circuits in series arranged in other semiconductor chips (see Japanese Patent Laid-open No. 2007-157266 (FIG. 2) referred to as Patent Document 7, for example). This related-art technology allows the automatic setting of chip identifiers from “0” sequentially for the layered semiconductor chips.